View NBC12429D_6259385.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2003 january, 2003 - rev. 2 1 publication order number: nbc12429/d nbc12429 3.3v/5vprogrammable pll synthesized clock generator 25 mhz to 400 mhz the nbc12429 is a general purpose, pll based synthesized clock source. the vco will operate over a frequency range of 200 mhz to 400 mhz. the vco frequency is sent to the n-output divider, where it can be configured to provide division ratios of 1, 2, 4, or 8. the vco and output frequency can be programmed using the parallel or serial interfaces to the configuration logic. output frequency steps of 1.0 mhz can be achieved using a 16 mhz crystal, depending on the output dividers. the pll loop filter is fully integrated and does not require any external components. ? best-in-class output jitter performance, 20 ps peak-to-peak ? 25 mhz to 400 mhz programmable differential pecl outputs ? fully integrated phase-lock-loop with internal loop filter ? parallel interface for programming counter and output dividers during power-up ? minimal frequency overshoot ? serial 3-wire programming interface ? crystal oscillator interface ? operating range: v cc = 3.135 v to 5.25 v ? cmos and ttl compatible control inputs ? drop-in replacement for motorola mc12429 marking diagrams a = assembly location wl = wafer lot yy = year ww = work week plcc-28 fn suffix case 776 nbc12429 awlyyww 128 lqfp-32 fa suffix case 873a nbc12429 awlyyww device package shipping ordering information nbc12429fn plcc-28 37 units/rail nbc12429fnr2 plcc-28 500 tape & reel nbc12429fa lqfp-32 250 units/tray nbc12429far2 lqfp-32 2000 tape & reel 1 32 http://onsemi.com
nbc12429 http://onsemi.com 2 9- bit sr 2- bit sr 3- bit sr 16 figure 1. nbc12429 block diagram (28-lead plcc) 10-20 mhz s_load p_load s_data s_clock xtal1 xtal2 osc 4 5 phase detector 28 7 9-bit m counter latch vco n (1, 2, 4, 8) latch 200-400 mhz f out f out +3.3 or 5.0 v 21, 25 24 23 v cc latch test 20 +3.3 or 5.0 v pll_v cc 1 mhz f ref 01 27 26 01 m[8:0] 9 8 ? 16 n[1:0] 2 17, 18 22, 19 oe 6 1 n[1] n[0] m[8] m[7] m[6] m[5] m[4] xtal1 nc nc pll_v cc s_load s_data s_clock figure 2. 28-lead plcc (top view) v cc fout fout gnd v cc gnd test xtal2 oe p_load m[0] m[1] m[2] m[3] figure 3. 32-lead lqfp (top view) n/c n[1] n[0] m[8] m[7] m[6] m[5] n/c n/c pll_v cc pll_v cc s_load s_data s_clock f out f out gnd v cc v cc gnd test oe p_load m[0] m[1] m[2] m[3] n/c m[4] xtal1 v cc xtal2 26 27 28 1 2 3 4 18 17 16 15 14 13 12 56 7891011 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 910111213141516 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25
nbc12429 http://onsemi.com 3 the following gives a brief description of the functionality of the nbc12429 inputs and outputs. unless explicitly stated, all inputs are cmos/ttl compatible with either pull-up or pulldown resistors. the pecl outputs are capable of driving two series terminated 50 transmission lines on the incident edge. pin function description pin name function description inputs xtal1, xtal2 crystal inputs these pins form an oscillator when connected to an external series-resonant crystal. s_load* cmos/ttl serial latch input (internal pulldown resistor) this pin loads the configuration latches with the contents of the shift registers. the latches will be transparent when this signal is high; thus, the data must be stable on the high-to-low transition of s_load for proper operation. s_data* cmos/ttl serial data input (internal pulldown resistor) this pin acts as the data input to the serial configuration shift registers. s_clock* cmos/ttl serial clock input (internal pulldown resistor) this pin serves to clock the serial configuration shift registers. data from s_data is sampled on the rising edge. p_load ** cmos/ttl parallel latch input (internal pullup resistor) this pin loads the configuration latches with the contents of the parallel inputs .the latches will be transparent when this signal is low; therefore, the parallel data must be stable on the low-to-high transition of p_load for proper opera- tion. m[8:0]** cmos/ttl pll loop divider inputs (internal pullup resistor) these pins are used to configure the pll loop divider. they are sampled on the low-to-high transition of p_load . m[8] is the msb, m[0] is the lsb. n[1:0]** cmos/ttl output divider inputs (internal pullup resistor) these pins are used to configure the output divider modulus. they are sampled on the low-to-high transition of p_load . oe** cmos/ttl output enable input (internal pullup resistor) active high output enable. the enable is synchronous to eliminate possibility of runt pulse generation on the fout output. outputs f out , f out pecl differential outputs these differential, positive-referenced ecl signals (pecl) are the outputs of the synthesizer. test cmos/ttl output the function of this output is determined by the serial configuration bits t[2:0]. power v cc positive supply for the logic the positive supply for the internal logic and output buffer of the chip, and is con- nected to +3.3 v or +5.0 v. pll_v cc positive supply for the pll this is the positive supply for the pll and is connected to +3.3 v or +5.0 v. gnd negative power supply these pins are the negative supply for the chip and are normally all connected to ground. * when left open, these inputs will default low. ** when left open, these inputs will default high.
nbc12429 http://onsemi.com 4 attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor 37.5 k esd protection human body model machine model charged device model > 2 kv > 150 v > 1 kv moisture sensitivity (note 1) plcc lqfp level 1 level 2 flammability rating oxygen index: 28 to 34 ul 94 v-0 @ 0.125 in transistor count 2035 meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. maximum ratings (note 2) symbol parameter condition 1 condition 2 rating unit v cc positive supply gnd = 0 v - 6 v v i input voltage gnd = 0 v v i v cc 6 v i out output current continuous surge - - 50 100 ma ma ta operating temperature range - - 0 to +70 c t stg storage temperature range - - -65 to +150 c ja thermal resistance (junction-to-ambient) 0 lfpm 500 lfpm 28 plcc 28 plcc 63.5 43.5 c/w c/w jc thermal resistance (junction-to-case) std bd 28 plcc 22 to 26 c/w ja thermal resistance (junction-to-ambient) 0 lfpm 500 lfpm 32 lqfp 32 lqfp 80 55 c/w c/w jc thermal resistance (junction-to-case) std bd 32 lqfp 12 to 17 c/w t sol wave solder < 2 to 3 sec @ 248 c - 265 c 2. maximum ratings are those values beyond which device damage may occur.
nbc12429 http://onsemi.com 5 dc characteristics (v cc = 3.3 v 5%) 0 c 25 c 70 c symbol characteristic condition min typ max min typ max min typ max unit v ih lvcmos/ lvttl input high voltage v cc = 3.3 v 2.0 - - 2.0 - - 2.0 - - v v il lvcmos/ lvttl input low voltage v cc = 3.3 v - - 0.8 - - 0.8 - - 0.8 v i in input current - - 1.0 - - 1.0 - - 1.0 ma v oh output high voltage test i oh = -0.8 ma 2.5 - - 2.5 - - 2.5 - - v v ol output low voltage test i ol = 0.8 ma - - 0.4 - - 0.4 - - 0.4 v v oh pecl output high voltage f out f out v cc = 3.3 v (notes 3, 4) 2.155 - 2.405 2.155 - 2.405 2.155 - 2.405 v v ol pecl output low voltage f out f out v cc = 3.3 v (notes 3, 4) 1.355 - 1.605 1.355 - 1.605 1.355 - 1.605 v i cc power supply current v cc pll_v cc 48 18 56 22 70 26 48 18 58 22 70 26 48 18 61 22 70 26 ma ma 3. f out /f out output levels will vary 1:1 with v cc variation. 4. f out /f out outputs are terminated through a 50 resistor to v cc - 2.0 v. dc characteristics (v cc = 5.0 v 5%) 0 c 25 c 70 c symbol characteristic condition min typ max min typ max min typ max unit v ih cmos/ ttl input high voltage v cc = 5.0 v 2.0 - - 2.0 - - 2.0 - - v v il cmos/ ttl input low voltage v cc = 5.0 v - - 0.8 - - 0.8 - - 0.8 v i in input current - - 1.0 - - 1.0 - - 1.0 ma v oh output high voltage test i oh = -0.8 ma 2.5 - - 2.5 - - 2.5 - - v v ol output low voltage test i ol = 0.8 ma - - 0.4 - - 0.4 - - 0.4 v v oh pecl output high voltage f out f out v cc = 5.0 v (notes 5, 6) 3.855 - 4.105 3.855 - 4.105 3.855 - 4.105 v v ol pecl output low voltage f out f out v cc = 5.0 v (notes 5, 6) 3.055 - 3.305 3.055 - 3.305 3.055 - 3.305 v i cc power supply current v cc pll_v cc 50 19 58 23 75 27 50 19 60 23 75 27 50 19 65 23 75 27 ma ma 5. f out /f out output levels will vary 1:1 with v cc variation. 6. f out /f out outputs are terminated through a 50 resistor to v cc - 2.0 volts.
nbc12429 http://onsemi.com 6 ac characteristics (v cc = 3.125 v to 5.25 v 5%; t a = 0 to 70 c) (note 8) symbol characteristic condition min max unit f maxi maximum input frequency s_clock xtal oscillator (note 7) - 10 10 20 mhz f maxo maximum output frequency vco (internal) f out 200 25 400 400 mhz t lock maximum pll lock time - 10 ms t jitter cycle-to-cycle jitter (1 ) see applications section - 20 ps t s setup time s_data to s_clock s_clock to s_load m, n to p_load 20 20 20 - - - ns t h hold time s_data to s_clock m, n to p_load 20 20 - - ns t pwmin minimum pulse width s_load p_load 50 50 - - ns dco output duty cycle 47.5 52.5 % t r , t f output rise/fall f out 20%-80% 175 425 ps 7. 10 mhz is the maximum frequency to load the feedback divide registers. s_clock can be switched at higher frequencies when use d as a test clock in test_mode 6. 8. f out /f out outputs are terminated through a 50 resistor to v cc - 2.0 v.
nbc12429 http://onsemi.com 7 functional description the internal oscillator uses the external quartz crystal as the basis of its frequency reference. the output of the reference oscillator is divided by 16 before being sent to the phase detector. with a 16 mhz crystal, this provides a reference frequency of 1 mhz. although this data sheet illustrates functionality only for a 16 mhz crystal, table 1, any crystal in the 10-20 mhz range can be used, table 3. the vco within the pll operates over a range of 200 to 400 mhz. its output is scaled by a divider that is configured by either the serial or parallel interfaces. the output of this loop divider is also applied to the phase detector. the phase detector and the loop filter force the vco output frequency to be m times the reference frequency by adjusting the vco control voltage. note that for some values of m (either too high or too low), the pll will not achieve loop lock. the output of the vco is also passed through an output divider before being sent to the pecl output driver. this output divider (n divider) is configured through either the serial or the parallel interfaces and can provide one of four division ratios (1, 2, 4, or 8). this divider extends the performance of the part while providing a 50% duty cycle. the output driver is driven differentially from the output divider and is capable of driving a pair of transmission lines terminated into 50 to v cc -2.0 v. the positive reference for the output driver and the internal logic is separated from the power supply for the phase-locked loop to minimize noise induced jitter. the configuration logic has two sections: serial and parallel. the parallel interface uses the values at the m[8:0] and n[1:0] inputs to configure the internal counters. normally upon system reset, the p_load input is held low until sometime after power becomes valid. on the low-to-high transition of p_load , the parallel inputs are captured. the parallel interface has priority over the serial interface. internal pullup resistors are provided on the m[8:0] and n[1:0] inputs to reduce component count in the application of the chip. the serial interface logic is implemented with a fourteen bit shift register scheme. the register shifts once per rising edge of the s_clock input. the serial input s_data must meet setup and hold timing as specified in the ac characteristics section of this document. with p_load held high, the configuration latches will capture the value of the shift register on the high-to-low edge of the s_load input. see the programming section for more information. the test output reflects various internal node values and is controlled by the t[2:0] bits in the serial data stream. see the programming section for more information. table 1. programming vco frequency function table vco freq ency 256 128 64 32 16 8 4 2 1 frequency (mhz) m count* m8 m7 m6 m5 m4 m3 m2 m1 m0 200 200 0 1 1 0 0 1 0 0 0 201 201 0 1 1 0 0 1 0 0 1 202 202 0 1 1 0 0 1 0 1 0 203 203 0 1 1 0 0 1 0 1 1 ? w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w 397 397 1 1 0 0 0 1 1 0 1 398 398 1 1 0 0 0 1 1 1 0 399 399 1 1 0 0 0 1 1 1 1 400 400 1 1 0 0 1 0 0 0 0 *with 16 mhz crystal.
nbc12429 http://onsemi.com 8 programming interface programming the nbc12429 is accomplished by properly configuring the internal dividers to produce the desired frequency at the outputs. the output frequency can by represented by this formula: fout (f xtal 16) m n (eq. 1) where f xtal is the crystal frequency, m is the loop divider modulus, and n is the output divider modulus. note that it is possible to select values of m such that the pll is unable to achieve loop lock. to avoid this, always make sure that m is selected to be 200 m 400 for a 16 mhz input reference. assuming that a 16 mhz reference frequency is used the above equation reduces to: fout m n (eq. 2) substituting the four values for n (1, 2, 4, 8) yields: table 2. programmable output divider function table n1 n0 n divider f out output frequency range (mhz)* 0 0 1 m 200-400 0 1 2 m 2 100-200 1 0 4 m 4 50-100 1 1 8 m 8 25-50 *for crystal frequency of 16 mhz. the user can identify the proper m and n values for the desired frequency from the above equations. the four output frequency ranges established by n are 200-400 mhz, 100-200 mhz, 50-100 mhz and 25-50 mhz, respectively. from these ranges, the user will establish the value of n required. the value of m can then be calculated based on equation 1. for example, if an output frequency of 131 mhz was desired, the following steps would be taken to identify the appropriate m and n values. 131 mhz falls within the frequency range set by an n value of 2; thus, n [1:0] = 01. for n = 2, f out = m 2 and m = 2 x f out . therefore, m = 131 x 2 = 262, so m[8:0] = 100000110. following this same procedure, a user can generate any whole frequency desired between 25 and 400 mhz. note that for n > 2, fractional values of f out can be realized. the size of the programmable frequency steps (and thus, the indicator of the fractional output frequencies achievable) will be equal to f xtal 16 n. for input reference frequencies other than 16 mhz, see table 3, which shows the usable vco frequency and m divider range. the input frequency and the selection of the feedback divider m is limited by the vco frequency range and f xtal . m must be configured to match the vco frequency range of 200 to 400 mhz in order to achieve stable pll operation. m min f vcomin (f xtal 16) and (eq. 3) m max f vcomax (f xtal 16) (eq. 4) the value for m falls within the constraints set for pll stability. if the value for m fell outside of the valid range, a different n value would be selected to move m in the appropriate direction. the m and n counters can be loaded either through a parallel or serial interface. the parallel interface is controlled via the p_load signal such that a low to high transition will latch the information present on the m[8:0] and n[1:0] inputs into the m and n counters. when the p_load signal is low, the input latches will be transparent and any changes on the m[8:0] and n[1:0] inputs will affect the f out output pair. to use the serial port, the s_clock signal samples the information on the s_data line and loads it into a 14 bit shift register. note that the p_load signal must be high for the serial load operation to function. the test register is loaded with the first three bits, the n register with the next two, and the m register with the final nine bits of the data stream on the s_data input. for each register, the most significant bit is loaded first (t2, n1, and m8). a pulse on the s_load pin after the shift register is fully loaded will transfer the divide values into the counters. the high to low transition on the s_load input will latch the new divide values into the counters. figures 4 and 5 illustrate the timing diagram for both a parallel and a serial load of the nbc12429 synthesizer. m[8:0] and n[1:0] are normally specified once at power-up through the parallel interface, and then possibly again through the serial interface. this approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. the test output provides visibility for one of the several internal nodes as determined by the t[2:0] bits in the serial configuration stream. it is not configurable through the parallel interface. the t2, t1, and t0 control bits are preset to `000' when p_load is low so that the pecl f out outputs are as jitter-free as possible. any active signal on the test output pin will have detrimental affects on the jitter of the pecl output pair. in normal operations, jitter specifications are only guaranteed if the test output is static. the serial configuration port can be used to select one of the alternate functions for this pin.
nbc12429 http://onsemi.com 9 table 3. nbc12429 frequency operating range vco frequency range for a crystal frequency of: output frequency for f xtal = 16 mhz and for n = m m[8:0] 10 12 14 16 18 20 1 2 4 8 160 010100000 200 170 010101010 212.5 180 010110100 202.5 225 190 0101 11110 213.75 237.5 200 011001000 200 225 250 200 100 50 25 210 011010010 210 236.25 262.5 210 105 52.5 26.25 220 011011100 220 247.5 275 220 110 55 27.5 230 011100110 201.25 230 258.75 287.5 230 115 57.5 28.75 240 011110000 210 240 270 300 240 120 60 30 250 011111010 218.75 250 281.25 312.5 250 125 62.5 31.25 260 100000100 227.5 260 292.5 325 260 130 65 32.5 270 100001110 202.5 236.25 270 303.75 337.5 270 135 67.5 33.75 280 100011000 210 245 280 315 350 280 140 70 35 290 100100010 217.5 253.75 290 326.25 362.5 290 145 72.5 36.25 300 100101100 225 262.5 300 337.5 375 300 150 75 37.5 310 100110110 232.5 271.25 310 348.75 387.5 310 155 77.5 38.75 320 101000000 200 240 280 320 360 400 320 160 80 40 330 101001010 206.25 247.5 288.75 330 371.25 330 165 82.5 41.25 340 101010100 212.5 255 297.5 340 382.5 340 170 85 42.5 350 101011110 218.75 262.5 306.25 350 393.75 350 175 87.5 43.75 360 101101000 225 270 315 360 360 180 90 45 370 101110010 231.25 277.5 323.75 370 370 185 92.5 46.25 380 101111100 237.5 285 332.5 380 380 190 95 47.5 390 110000110 243.75 292.5 341.25 390 390 195 97.5 48.75 400 110010000 250 300 350 400 400 200 100 50 410 110011010 256.25 307.5 358.75 420 110100100 262.5 315 367.5 430 110101110 268.75 322.5 376.25 440 110111000 275 330 385 450 111000010 281.25 337.5 393.75 460 111001100 287.5 345 470 111010110 293.75 352.5 480 111100000 300 360 490 111101010 306.25 367.5 500 1111 10100 312.5 375 510 111111110 318.75 382.5
nbc12429 http://onsemi.com 10 most of the signals available on the test output pin are useful only for performance verification of the nbc12429 itself. however, the pll bypass mode may be of interest at the board level for functional debug. when t[2:0] is set to 110, the nbc12429 is placed in pll bypass mode. in this mode the s_clock input is fed directly into the m and n dividers. the n divider drives the f out differential pair and the m counter drives the test output pin. in this mode the s_clock input could be used for low speed board level functional test or debug. bypassing the pll and driving f out directly gives the user more control on the test clocks sent through the clock tree. figure 6 shows the functional setup of the pll bypass mode. because the s_clock is a cmos level the input frequency is limited to 250 mhz or less. this means the fastest the f out pin can be toggled via the s_clock is 250 mhz as the minimum divide ratio of the n counter is 1. note that the m counter output on the test output will not be a 50% duty cycle due to the way the divider is implemented. t2 t1 t0 test (pin 20) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 shift register out high f ref m counter out f out low pll bypass f out 4 figure 4. parallel interface timing diagram m[8:0] n[1:0] p_load m, n figure 5. serial interface timing diagram s_clock s_data s_load t2 t1 t0 n1 n0 m8 m7 m6 m5 m4 m3 m2 m1 m0 first bit last bit figure 6. serial test clock block diagram fdiv4 mcnt low fout mcnt fref high test mux 7 0 test fout (via enable gate) n (1, 2, 4, 8) 0 1 pll 12429 latch reset pload m counter sload t0 t1 t2 vco_clk shift reg 14- bit decode sdata sclock mcnt fref sel_clk ? t2=t1=1, t0=0: test mode ? sclock is selected, mcnt is on test output, sclock n is on fout pin. pload acts as reset for test pin latch. when latch reset, t2 data is shifted out test pin.
nbc12429 http://onsemi.com 11 applications information using the on-board crystal oscillator the nbc12429 features a fully integrated on-board crystal oscillator to minimize system implementation costs. the oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. the series resonant design provides better stability and eliminates the need for large on chip capacitors. the oscillator is totally self contained so that the only external component required is the crystal. as the oscillator is somewhat sensitive to loading on its inputs, the user is advised to mount the crystal as close to the nbc12429 as possible to avoid any board level parasitics. to facilitate co-location, surface mount crystals are recommended, but not required. because the series resonant design is affected by capacitive loading on the crystal terminals, loading variation introduced by crystals from different vendors could be a potential issue. for crystals with a higher shunt capacitance, it may be required to place a resistance across the terminals to suppress the third harmonic. although typically not required, it is a good idea to layout the pcb with the provision of adding this external resistor. the resistor value will typically be between 500 and 1 k . the oscillator circuit is a series resonant circuit and thus, for optimum performance, a series resonant crystal should be used. unfortunately, most crystals are characterized in a parallel resonant mode. fortunately, there is no physical difference between a series resonant and a parallel resonant crystal. the difference is purely in the way the devices are characterized. as a result, a parallel resonant crystal can be used with the nbc12429 with only a minor error in the desired frequency. a parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified (a few hundred ppm translates to khz inaccuracies). in a general computer application, this level of inaccuracy is immaterial. table 4 below specifies the performance requirements of the crystals to be used with the nbc12429. table 4. crystal specifications parameter value crystal cut fundamental at cut resonance series resonance* frequency tolerance 75 ppm at 25 c frequency/temperature stability 150 ppm 0 to 70 c operating range 0 to 70 c shunt capacitance 5-7 pf equivalent series resistance (esr) 50 to 80 correlation drive level 100 w aging 5 ppm/yr (first 3 years) * see accompanying text for series versus parallel resonant discussion. power supply filtering the nbc12429 is a mixed analog/digital product and as such, it exhibits some sensitivities that would not necessarily be seen on a fully digital product. analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. the nbc12429 provides separate power supplies for the digital circuitry (v cc ) and the internal pll (pll_v cc ) of the device. the purpose of this design technique is to try and isolate the high switching noise of the digital outputs from the relatively sensitive internal analog phase-locked loop. in a controlled environment such as an evaluation board, this level of isolation is sufficient. however, in a digital system environment where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. the simplest form of isolation is a power supply filter on the pll_v cc pin for the nbc12429. figure 7 illustrates a typical power supply filter scheme. the nbc12429 is most susceptible to noise with spectral content in the 1 khz to 1 mhz range. therefore, the filter should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc voltage drop that will be seen between the v cc supply and the pll_v cc pin of the nbc12429. from the data sheet, the pll_v cc current (the current sourced through the pll_v cc pin) is typically 23 ma (27 ma maximum). assuming that a minimum of 2.8 v must be maintained on the pll_v cc pin, very little dc voltage drop can be tolerated when a 3.3 v v cc supply is used. the resistor shown in figure 7 must have a resistance of 10-15 to meet the voltage drop criteria. the rc filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 khz. as the noise frequency crosses the series resonant point of an individual capacitor, it's overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. figure 7. power supply filter pll_v cc v cc nbc12429 0.01 f 22 f l=1000 h r=15 0.01 f 3.3 v or 5.0 v r s = 10-15 3.3 v or 5.0 v
nbc12429 http://onsemi.com 12 a higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. figure 7 shows a 1000 h choke. this value choke will show a significant impedance at 10 khz frequencies and above. because of the current draw and the voltage that must be maintained on the pll_v cc pin, a low dc resistance inductor is required (less than 15 ). generally, the resistor/capacitor filter will be cheaper, easier to implement, and provide an adequate level of supply filtering. the nbc12429 provides sub-nanosecond output edge rates and therefore a good power supply bypassing scheme is a must. figure 8 shows a representative board layout for the nbc12429. there exists many different potential board layouts and the one pictured is but one. the important aspect of the layout in figure 8 is the low impedance connections between v cc and gnd for the bypass capacitors. combining good quality general purpose chip capacitors with good pcb layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the nbc12429 outputs. it is imperative that low inductance chip capacitors are used. it is equally important that the board layout not introduce any of the inductance saved by using the leadless capacitors. thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. figure 8. pcb board layout for nbc12429 (28 plcc) c2 1 c3 r1 xtal c1 c1 r1 = 10-15 c1 = 0.01 f c2 = 22 f c3 = 0.1 f = v cc = gnd = via note the dotted lines circling the crystal oscillator connection to the device. the oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. it is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on-board oscillator. note the provisions for placing a resistor across the crystal oscillator terminals as discussed in the crystal oscillator section of this data sheet. although the nbc12429 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential pll), there still may be applications in which overall performance is being degraded due to system power supply noise. the power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise-related problems in most designs.
nbc12429 http://onsemi.com 13 jitter performance of the nbc12429 jitter is a common parameter associated with clock generation and distribution. clock jitter can be defined as the deviation in a clock's output transition from its ideal position. cycle-to-cycle jitter (short-term) is the period variation between two adjacent cycles over a defined number of observed cycles. the number of cycles observed is application dependent but the jedec specification is 1000 cycles. figure 9. cycle-to-cycle jitter t jitter(cycle- cycle) = t 1 - t 0 t 0 t 1 peak-to-peak jitter is the difference between the highest and lowest acquired value and is represented as the width of the gaussian base. figure 10. peak-to-peak jitter time typical gaussian distribution rms or one sigma jitter jitter amplitude peak-to-peak jitter (6 sigma) there are different ways to measure jitter and often they are confused with one another. the typical method of measuring jitter is to look at the timing signal with an oscilloscope and observe the variations in period-to-period or cycle-to-cycle. if the scope is set up to trigger on every rising or falling edge, set to infinite persistence mode and allowed to trace sufficient cycles, it is possible to determine the maximum and minimum periods of the timing signal. digital scopes can accumulate a large number of cycles, create a histogram of the edge placements and record peak-to-peak as well as standard deviations of the jitter. care must be taken that the measured edge is the edge immediately following the trigger edge. these scopes can also store a finite number of period durations and post-processing software can analyze the data to find the maximum and minimum periods. recent hardware and software developments have resulted in advanced jitter measurement techniques. the tektronix tds-series oscilloscopes have superb jitter analysis capabilities on non-contiguous clocks with their histogram and statistics capabilities. the tektronix tdsjit2/3 jitter analysis software provides many key timing parameter measurements and will extend that capability by making jitter measurements on contiguous clock and data cycles from single-shot acquisitions. m1 by amherst was used as well and both test methods correlated. this test process can be correlated to earlier test methods and is more accurate. all of the jitter data reported on the nbc12429 was collected in this manner. figure 11 shows the jitter as a function of the output frequency. the graph shows that for output frequencies from 25 to 400 mhz the jitter falls within the 20 ps peak-to-peak specification. the general trend is that as the output frequency is increased, the output edge jitter will decrease. figure 12 illustrates the rms jitter performance of the nbc12429 across its specified vco frequency range. note that the jitter is a function of both the output frequency as well as the vco frequency. however, the vco frequency shows a much stronger dependence. the data presented has not been compensated for trigger jitter. long-term period jitter is the maximum jitter observed at the end of a period's edge when compared to the position of the perfect reference clock's edge and is specified by the number of cycles over which the jitter is measured. the number of cycles used to look for the maximum jitter varies by application but the jedec spec is 10,000 observed cycles. the nbc12429 exhibits long term and cycle-to-cycle jitter, which rivals that of saw based oscillators. this jitter performance comes with the added flexibility associated with a synthesizer over a fixed frequency oscillator. the jitter data presented should provide users with enough information to determine the effect on their overall timing budget. the jitter performance meets the needs of most system designs while adding the flexibility of frequency margining and field upgrades. these features are not available with a fixed frequency saw oscillator.
nbc12429 http://onsemi.com 14 figure 11. rms jitter vs. vco frequency vco frequency (mhz) 200 250 300 350 400 25 20 15 10 5 0 rms jitter (ps) n = 1 n = 8 n = 2 n = 4 figure 12. rms jitter vs. output frequency 25 20 15 10 5 0 rms jitter (ps) 400 350 300 250 200 150 100 50 output frequency (mhz)
nbc12429 http://onsemi.com 15 t set- up t hold s_clock s_data figure 13. set-up and hold t set- up t hold s_load s_data figure 14. set-up and hold t set- up t hold p_ load m[8:0] figure 15. set-up and hold t period pulse width f out f out figure 16. output duty cycle n[1:0] dco pw period
nbc12429 http://onsemi.com 16 v tt = v cc - 2.0 v figure 17. typical termination for output driver and device evaluation (see application note and8020 - termination of ecl logic devices.) driver device receiver device d 50 50 v tt f out d f out
nbc12429 http://onsemi.com 17 package dimensions plcc-28 fn suffix plastic plcc package case 776-02 issue e -n- -m- -l- v w d d y brk 28 1 view s s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s l-m m 0.007 (0.180) n s t -t- b s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t u s l-m m 0.007 (0.180) n s t z g1 x view d-d s l-m m 0.007 (0.180) n s t k1 view s h k f s l-m m 0.007 (0.180) n s t notes: 1. datums -l-, -m-, and -n- determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum -t-, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). dim min max min max millimeters inches a 0.485 0.495 12.32 12.57 b 0.485 0.495 12.32 12.57 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 --- 0.51 --- k 0.025 --- 0.64 --- r 0.450 0.456 11.43 11.58 u 0.450 0.456 11.43 11.58 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y --- 0.020 --- 0.50 z 2 10 2 10 g1 0.410 0.430 10.42 10.92 k1 0.040 --- 1.02 ---
nbc12429 http://onsemi.com 18 package dimensions lqfp-32 fa suffix plastic lqfp package case 873a-02 issue a detail y a s1 v b 1 8 9 17 25 32 ae ae p detail y base n j d f metal section ae-ae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad detail ad a1 b1 v1 4x s 4x 9 -t- -z- -u- t-u 0.20 (0.008) z ac t-u 0.20 (0.008) z ab 0.10 (0.004) ac -ac- -ab- m 8x -t-, -u-, -z- t-u m 0.20 (0.008) z ac notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -ab- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -t-, -u-, and -z- to be determined at datum plane -ab-. 5. dimensions s and v to be determined at seating plane -ac-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -ab-. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref
nbc12429 http://onsemi.com 19 notes
nbc12429 http://onsemi.com 20 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. typicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 2-9-1 kamimeguro, meguro-ku, tokyo, japan 153-0051 phone : 81-3-5773-3850 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nbc12429/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 800-282-9855 toll free usa/canada

▲Up To Search▲

Price & Availability of NBC12429D

	To Download NBC12429D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .